1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having an improved trench isolation structure.
2. Discussion of Related Art
As the integration of a semiconductor device increases, a very fine pattern is required or fabricating the semiconductor device. Also, the channel length of the transistor and the width of a field oxidation layer for device isolation are reduced. Accordingly, various device isolation methods such as LOCOS, modified LOCOS, or trench isolation methods have been developed.
FIGS. 1 to 6 illustrate a conventional semiconductor device isolation method applying the trench isolation technique. Such method is described in the following six steps.
In the first step, as illustrated in FIG. 1, a first insulating layer 12 of a heat-oxidation layer and a first anti-oxidation layer 14 of a nitride layer are sequentially formed on the semiconductor substrate, for example, the silicon substrate 10. A photoresist pattern (not shown) is formed thereon, excluding the surface of the first anti-oxidation layer 14 of a non-active region. Here, the first insulating layer 12 is formed in the range of 120 to 180 .ANG. in thickness and the fist anti-oxidation layer 14 is formed in the range of 1300 to 1700 .ANG. in thickness. Thereafter, the first anti-oxidation layer 14 and the first insulating layer 12 are sequentially etched to expose the surface of the substrate of the non-active region, using the photoresist pattern as a mask. Next, photoresist pattern is removed; leaving the first anti-oxidation layer 14 and the first insulating layer 12 only on the active region where an active device will be formed. Then, a trench 11 is formed by partially etching the exposed surface of the substrate 10, using the etched first anti-oxidation layer 14 as a mask.
In the second step, as illustrated in FIG. 2, a second insulating layer 16 of a thermal oxidation layer is formed along the inner surface of the trench. Here, the second insulating layer 16 is formed in the range of 200 to 300 .ANG. in thickness. The second insulating layer 16 is formed inside the trench to cure the damage on the etched surface of the silicon substrate 10 caused by the etching process for forming the trench.
In the third step, as illustrated in FIG. 3, a second anti-oxidation layer (namely, a nitride liner) 18 is formed on the substrate in the range of 60 to 150 .ANG. in thickness. A third insulating layer 20 of an oxide layer is deposited on the second anti-oxidation layer 18, and completely fills the trench in the range of 5000 to 6000 .ANG. in thickness.
If the silicon on the side wall of the trench is oxidized and expanded in volume due to the following oxidation process after formation of trench isolation, a dislocation in the substrate can be caused by stress applied to the silicon substrate. Second anti-oxidation layer 18 is formed between the second insulating layer 16 along the inner surface of trench and the third insulating layer 20 to prevent O.sub.2 from passing through the third insulating layer 20 filled in the trench to the side wall of the trench in order to reduce the stress caused from the expansion in volume.
In the fourth step, as illustrated in FIG. 4, the third insulating layer 20 and the first and second anti-oxidation layers 14 and 18 are planarized by a chemical mechanical polishing (CMP) process.
In the fifth step, as illustrated in FIG. 5, the first anti-oxidation layer 14 is removed by using an isotropic etching process. In this step, the second anti-oxidation layer 18 is also partially etched.
In the sixth step, as illustrated in FIG. 6, the first insulating layer 12 on the active region and a predetermined upper portion of the third insulating layer 20 on the non-active region are etched by using a wet cleaning process to form trench isolation made of the second anti-oxidation layer 18 and the second and third insulating layers 16 and 20. Thereafter, a buffer oxidation layer (not shown) is formed on the active region of the substrate 10. Ion implantation processes for forming a well and for controlling the threshold voltage Vth are performed and the buffer oxidation layer is removed, completing the device isolation process.
But, with the above-mentioned device isolation method, the second anti-oxidation layer 18 has the following problems.
If the second oxidation layer 18 is made in the range of 60 to 150 .ANG. in thickness as described above, a concave groove, the part "I" in the drawing, is generated between the second and third insulating layers 16 and 20, i.e., in the junction area of the active region and the non-active region. As illustrated in FIG. 5, the groove is generated because when the first anti-oxidation layer 14 on the active region is etched, the second anti-oxidation layer 18 on the side of the third insulating layer 20 and in the trench is also partially etched at the same time. This problem is more severe when the first insulating layer 12 and the upper portion of the third insulating layers 20 are etched. If the groove is formed on a predetermined portion of the edges of trench isolation, the polysilicon remains partially on this part during the polysilicon layer etching process for forming a gate electrode. And consequently it brings about shorts in the gate electrode, causing undesired characteristics.
If the second anti-oxidation layer 18 is formed below 50 .ANG. in thickness to avoid this problem, it is difficult to cut off O.sub.2 being passed to the side wall of the trench by using the second anti-oxidation layer during the following oxide process (for example, processes of forming a buffer oxidation layer for ion implantation, the gate insulating layer and the oxidation layer on the surface of the gate electrode). Accordingly, with the silicon on the side wall of the trench being partially oxidized, the stress is applied to the silicon substrate because of the expansion in volume and thus the silicon lattice on the side wall of the trench are twisted. This induces a dislocation in the silicon substrate and generates more defects in the subsequent process step in the junction area. This causes a leakage current, and consequently decreases the total operational characteristic of the transistor.
In short, with a thin anti-oxidation layer employed to reduce the stress applied because of the expansion in volume, it is difficult to cut off the penetration of O.sub.2 to the side wall of the trench and thus the side wall of the trench can be oxidized. On the other hand, with a thick anti-oxidation layer, the second anti-oxidation layer is also partially etched during the step of isotropically etching the first anti-oxidation layer 14 used as a mask for the trench. As a result, groove is generated in this part. Consequently, a need exists for an improved method of fabricating trench isolation structure without these problems.